An Ecole Polytechnique Federale de Lausanne (EPFL) lab has come up with a new type of logic diagram and related optimization methods, that can be used to design computer chips with a nearly 20% gain in energy efficiency, speed or size. The lab has just entered into a license agreement with Synopsys, a global leader in electronic design automation and chip fabrication software.
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EPFL lab develops method for designing lower-power circuits
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